At present, non-volatile memories integrate, in the same substrate, memory cells and transistors fabricated simultaneously and hereinafter referred to in general as "devices". For this purpose, various methods are known and which, subsequent to defining the active areas, consist in implanting isolating regions; growing the field oxide; depositing a first polycrystalline silicon (polysilicon) layer; effecting a first shaping (definition) of the first polysilicon layer; depositing an intermediate dielectric layer (dielectric interpoly); removing the dielectric interpoly from the circuit areas not accommodating memory cells; depositing a second polysilicon layer; defining the gate regions in the transistors and memory cells; implanting source and drain; and, finally protecting and interconnecting the devices.
In recent years, for integrated circuit transistors in general, a so-called ITLDD (Inverse T Low Doped Drain) structure has been devised, which has the advantage of withstanding the hot electron injection stress typical of submicrometer structures. For this reason, the ITLDD structure is among the most favored for transistors with gate lengths below 0.5 .mu.m, but presents serious difficulties in terms of production and industrialization, as outlined below.
The first proposal for such a structure appeared in 1986 (cf. articles by Huang. T. Y. and others entitled "A novel submicron LDD transistor with inverse-T gate structure" IEEE-IEDM 1986, p. 742, and "A new LDD transistor with inverse-T gate structure" IEEE Electron Dev. Letters, 8, 1987, p. 151). These deal with a standard transistor in which the etching for defining the gate region is stopped at a certain level to give the desired structure, but not without obvious problems in terms of etching controllability and repeatability. So much so that, in the second of the above articles, alternative solutions are outlined for simplifying the etching stage, and, in a follow-up proposal, recourse is made by the same writer to two distinct gates, one wider and the other narrower, contacted by polysilicon spacers.
An alternative to the above process is described, for example, in an article by Izawa, R. and others entitled "Impact of the Gate-Drain Overlapped Device (GOLD) for deep submicrometer VLSI" IEEE Transactions Elect. Dev. 35, 1988, p. 2088. According to this process, which was later to become widely used, a first thin polysilicon layer is deposited; a very thin layer of native oxide (5-10.ANG.) is grown by exposure to air; a second polysilicon layer is deposited on the oxide layer; the second polysilicon layer is etched highly selectively, so as to stop at the thin oxide layer; the low-doped regions are implanted through the native oxide layer, the first polysilicon layer and the gate oxide layer; an LPCVD (Low Pressure Chemical Vapor Deposition) oxide layer is deposited and etched to define the lateral spacers; the first thin polysilicon layer is etched; partial lateral re-oxidation of the thin polysilicon layer is effected; and the high-doped regions are implanted. In this way, overlapping of the transistor gate region and the low-doped regions does not depend on the size of the spacers.
The above known process is especially critical as regards selective etching of the second polysilicon layer, which requires extremely selective technology (100 to 1 is the figure mentioned) for selecting between the polysilicon and oxide if the etching process is to be repeatable uniformly on a silicon wafer. What is more, no direct contact exists between the gate region parts separated by the native oxide layer, which, albeit thin, could impair electrical continuity. Finally, precise control of the lateral oxidation length of a doped polysilicon layer is not as straightforward as it would at first appear.
To overcome the above drawbacks, further processes have been proposed, such as that described in an article by Pfiester, J. and others entitled "A self-aligned LDD/channel implanted ITLDD process with selectively-deposited poly gates for CMOS VLSI" IEEE-IEDM, 1989, p. 253). This consists in forming the gate regions inside openings in an appropriate oxide layer over the first polysilicon layer; removing the oxide layer; implanting the low-doped regions: forming oxide spacers; and implanting the high-doped regions.
The process described in an article by Moon, J. E. and others entitled "A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS)" IEEE Electron Dev. Letters, 11, 1990, p. 221, consists in forming appropriately thick polysilicon spacers for electrically contacting the top part of the gate region, formed from a thick polysilicon layer, and the bottom part of the gate region, formed from a thin polysilicon layer and separated from the first by an oxide layer. In this case, the low-doped regions are implanted through the oxide and thin polysilicon layers prior to forming the spacers, and the high-doped regions are implanted after they are formed.
In the process described in an article by Wen, D. S. and others entitled "A Self-Aligned Inverse T Fully Overlapped LDD Device for Sub-Half Micron CMOS" IEEE-IEDM, 1989, p. 765, the problem of contacting the two parts of the gate region is solved by depositing a thin polysilicon layer after defining the thicker part of the gate region and before defining the oxide for the spacers, which obviously complicates the process by introducing additional deposits and etching. In this case also, a dummy oxide or TiN layer is used for arresting etching of the polysilicon in the thicker part of the gate region, thus resulting in selectivity problems, especially when overetching.
Other processes proposed for fully overlapping the gate region and low-doped regions (cf. the article by Hori, T. and others entitled "A New Submicron MOSFET With LATID (Large-Tilt Angle Implanted Drain) Structure" Int. Symp. VLSI Technology Dig. 1988, p. 15) consist in implanting the above regions by sharply tilting the beam and semiconductor wafer. Such a technique presents difficulties in controlling the junction profile, and, what is more, results in direct injection of the charge into the gate oxide.
All the above processes (and others not mentioned) have met with only a limited amount of success, due to the manufacturing difficulties involved, and at any rate are limited in scope to integrated circuit transistors in general.
Undoubtedly, an inverse-T profile as proposed is disadvantageous as regards capacitive coupling of the gate and drain regions, and detrimental to the speed of the device. Nevertheless, analysis of the structure has shown advantages are to be afforded by using such a profile for the gate region. Some of the above articles in fact show how optimizing dosage of the low-doped regions and overlap length may minimize the above drawback and so limit the theoretical coupling increase to 10%, the consequences of which are further reduced by virtue of a big improvement in the source and drain series resistance values.